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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ADUC814 microconverter , small package 12-bit adc with embedded flash mcu features analog i/o 6-channel 247 ksps adc 12-bit resolution adc high speed data capture mode programmable reference via on-chip dac for low level inputs adc performance down to v ref of 0.1 v dual-voltage output dacs 12-bit resolution, 15 s settling time memory 8 kbytes on-chip flash/ee program memory 640 bytes on-chip flash/ee data memory flash/ee, 100-year retention, 100 k cycles endurance three levels of flash/ee program memory security in-circuit serial download (no external hardware required) 256 bytes on-chip data ram 8051 based core 8051 compatible instruction set 32 khz external crystal on-chip programmable pll (16.78 mhz max) three 16-bit timer/counters 11 programmable i/o lines 11 interrupt sources, two priority levels power specified for 3 v and 5 v operation normal: 3 ma @ 3 v (core clk = 2.1 mhz) power-down: 15 a at 3 v (32 khz running) on-chip peripherals power-on reset circuit (no need for external por device) temperature monitor ( 1.5 c) precision voltage reference time interval counter (wake-up/rtc timer) uart serial i/o spi ? /i 2 c ? compatible serial i/o watchdog timer (wdt) and power supply monitor (psm) package and temperature range 28-lead tssop 4.4 mm 9.7 mm body package fully specified for C40 c to +125 c operation applications optical networkinglaser power control base station systemspower amplifier bias control precision instruments and smart sensors battery-powered systems and general precision system monitors functional block diagram microconverter is a registered trademark of analog devices, inc. spi is a registered trademark of motorola inc. i 2 c is a registered trademark of phillips corporation. quickstart is a trademark of analog devices, inc. windows is a registered trademark of microsoft corporation. general description the ADUC814 is a fully integrated 247 ksps 12-bit data acquisi- tion system incorporating a high performance multichannel adc, an 8-bit mcu, and program/data flash/ee memory on a single chip. this low power device operates from a 32 khz crystal with an on-chip pll generating a high frequency clock of 16.78 mhz. this clock is in turn routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the microcontroller core is an 8052 and is therefore 8051- instruction-set compatible. 8 kbytes of nonvolatile flash/ee program memory are provided on-chip. 640 bytes of nonvolatile flash/ee data memory and 256 bytes of ram are also integrated on-chip. the ADUC814 also incorporates additional analog function ality with dual 12-bit dacs, a power supply monitor, and a band gap reference. on-chip factory firmware supports in-circuit serial download and debug modes (via uart), as well as the single-pin emulation mode via the dload pin. the ADUC814 is supported by a quickstart d evelopment system. this is a full featured low cost system, consisting of pc-based (windows compatible) hardware and software development tools. the part operates from a single 3 v or 5 v supply over the extended temperature range ?0 c to +125 c. when operating from 3 v supplies, the power dissipation for the part is below 10 mw. the ADUC814 is housed in a 28-lead tssop package. ADUC814 prog. clock divider xtal2 xtal1 t/h ain mux temp mo nitor internal band gap vref ain0 vref cref ain5 osc and pll dac1 buf dac0 buf dac0 dac1 dac cont rol l ogic 12-bit adc adc cont rol l ogic buf power- on reset 8 kbytes flash/ee program memory 640 bytes flash/ee data memory 256 bytes user ram 3 16-bit timer/counters 1 wake-up/rtc timer 8051-based mcu with additional peripherals on-chip monitors power supply monitor watchdog timer uart and spi serial i/o 10 digital i/o pins
rev. 0 ?2? ADUC814especifications 1 parameter v dd = 5 v v dd = 3 v unit test conditions adc channel specifications a grade dc accuracy 2, 3 f sample = 147 khz resolution 12 12 bits integral nonlinearity
rev. 0 ?3? ADUC814 parameter v dd = 5 v v dd = 3 v unit test conditions dac channel specifications dac load to agnd r l = 10 k ? ? ?
rev. 0 ?4? ADUC814 parameter v dd = 5 v v dd = 3 v unit test conditions sclock and reset only 13 (schmitt-triggered inputs) v t+ 1.3 0.95 v min 3.0 2.5 v max v te 0.8 0.4 v min 1.4 1.1 v max v t+ e v te 0.3 0.3 v min 0.85 0.85 v max input currents p1.2ep1.7, dload ss int0 i 100 100 sii ci 100 100 tici 100 100 st sciictions
rev. 0 ?5? ADUC814 parameter v dd = 5 v v dd = 3 v unit test conditions start-up time (continued) oscillator powered down 15 osc_pd bit = 1 in pllcon wake-up with spi/i 2 c interrupt 150 400 ms typ wake-up with tic interrupt 150 400 ms typ wake-up with external reset 150 400 ms typ after external reset in normal mode 3 3 ms typ after wdt reset in normal mode 3 3 ms typ controlled via wdcon flash/ee memory reliability characteristics 16 endurance 17 100,000 100,000 cycles min data retention 18 100 100 years min power requirements 19, 20 power supply voltages av dd /dv dd e agnd 2.7 v min av dd /dv dd = 3 v nominal 3.3 v max 4.5 v min av dd /dv dd = 5 v nominal 5.5 v max power supply currents e normal mode dv dd current 13 5 2.5 ma max core clk = 2.097 mhz (cd bits in pllcon = 3) 42 ma typ av dd current 13 1.7 1.7 ma max dv dd current 20 10 ma max core clk = 16.78 mhz (max) 16 8 ma typ (cd bits in pllcon = 0) av dd current 1.7 1.7 ma max dv dd current 13 3.5 1.5 ma max core clk = 131.2 khz (min) 2.8 1.2 ma typ (cd bits in pllcon = 7) av dd current 1.7 1.7 ma max power supply currents e idle mode dv dd current 13 1.7 1.2 ma max core clk = 2.097 mhz (cd bits in pllcon = 3) 1.5 1 ma typ av dd current 13 0.15 0.15 ma max dv dd current 13 63 ma max core clk = 16.78 mhz (max) 4 2.5 ma typ (cd bits in pllcon = 0) av dd current 13 0.15 0.15 ma max dv dd current 13 1.25 1 ma max core clk = 131 khz (min) 1.1 0.7 ma typ (cd bits in pllcon = 7) av dd current 13 0.15 0.15 ma max power supply currents e power-down mode core clk = 2.097 mhz or 16.78 mhz (cd bits in pllcon = 3 or 0) dv dd current 13 20
rev. 0 ?6? ADUC814 specifications (continued) notes 1 temperature range e40?c to +125?c. 2 adc linearity is guaranteed when operating in nonpipelined mode, i.e., adc conversion followed sequentially by a read of the ad c result. adc linearity is also guaranteed during normal microconverter core operation. 3 adc lsb size = v ref /2^12, i.e., for 2.5 v, 1 lsb = 610 ?
rev. 0 ADUC814 ?7? timing specifications 1, 2, 3 (av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; all specifications t min to t max , unless otherwise noted.) 32.768 khz external crystal parameter min typ max unit figure clock input (external clock driven xtal1) t ck xtal1 period 30.52
rev. 0 ?8? ADUC814 16.78 mhz core_clk variable core_clk parameter min typ max min typ max unit figure uart timing (shift register mode) t xlxl serial port clock cycle time 715 12t core
rev. 0 ADUC814 ?9? parameter min typ max unit figure spi master mode timing (cpha = 1) t sl sclock low pulsewidth * 630 ns 4 t sh sclock high pulsewidth * 630 ns 4 t dav data output valid after sclock edge 50 ns 4 t dsu data input setup time before sclock edge 100 ns 4 t dhd data input hold time after sclock edge 100 ns 4 t df data output fall time 10 25 ns 4 t dr data output rise time 10 25 ns 4 t sr sclock rise time 10 25 ns 4 t sf sclock fall time 10 25 ns 4 * characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 in pllcon sfr set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 mh z. b. spi bit rate selection bits spr1 and spr0 in spicon sfr set to 0 and 0, respectively. sclock (cpo l = 0) t sh sclock (cpo l = 1) mosi miso msb in bits 6e1 bits 6e1 lsb in lsb msb t sl t dav t df t dr t sr t sf t dhd t dsu figure 4. spi master mode timing (cpha = 1)
rev. 0 ?10? ADUC814 parameter min typ max unit figure spi master mode timing (cpha = 0) t sl sclock low pulsewidth * 630 ns 5 t sh sclock high pulsewidth * 630 ns 5 t dav data output valid after sclock edge 50 ns 5 t dosu data output setup before sclock edge 150 ns 5 t dsu data input setup time before sclock edge 100 ns 5 t dhd data input hold time after sclock edge 100 ns 5 t df data output fall time 10 25 ns 5 t dr data output rise time 10 25 ns 5 t sr sclock rise time 10 25 ns 5 t sf sclock fall time 10 25 ns 5 * characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 in pllcon sfr set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 mh z. b. spi bit rate selection bits spr1 and spr0 in spicon sfr set to 0 and 0, respectively. sclock (cpo l = 0) t dsu sclock (cpo l = 1) mosi miso msb lsb lsb in bits 6e1 bits 6e1 msb in t dhd t dr t dav t df t dosu t sh t sl t sr t sf figure 5. spi master mode timing (cpha = 0) timing specifications (continued)
rev. 0 ADUC814 ?11? parameter min typ max unit figure spi slave mode timing (cpha = 1) t ss ss scoc 0 s scoc 0 s scoc 0 v ovscoc 0 s istscoc 100 itscoc 100 ot 10 ot 10 s scoct 10 s scoct 10 ss ss scoc 0 scoc co 0 ss scoc co 1 iso osi ss sin its 1 sin s its 1 s s s s v s s ss sistc1
rev. 0 ?12? ADUC814 parameter min typ max unit figure spi slave mode timing (cpha = 0) t ss ss scoc 0 s scoc 0 s scoc 0 v ovscoc 0 s istscoc 100 itscoc 100 ot 10 ot 10 s scoct 10 s scoct 10 ss ss scoc 0 oss ov ss 0 ss ss scoc 0 iso osi scoc co 1 scoc co 0 s its1 s its1 sin sin s v oss s s ss s s ss ss sistc0
rev. 0 ADUC814 ?13? absolute maximum ratings 1 (t a = 25 convst int1 int0 n v c 1c 1c 1cc0 1cc1 v t t1 scoc t1 ss tc iso osi oini t o c1 0 ? ? ? ? ? ? ? ? ?
rev. 0 ?14? ADUC814 pin no. mnemonic type * function 1 dgnd s digital ground. ground reference point for the digital circuitry. 2d load i enables debug/serial download mode when pulled high through a resistor on power-on or reset. in this mode, dload may also be used as an external emulation i/o pin, and therefore, the voltage level at this pin must not be changed during this mode of operation since it may cause an emulation interrupt that will halt code execution. user code is executed when this pin is pulled low on power-on or reset. 3-7 p3.0ep3.4 i/o p3.0ep3.4 are bidirectional port pins with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state, can be used as inputs. as inputs, port 3 pins being pulled externally low will source current because of the internal pull-up resistors. when driving a 0-to-1 output transition, a strong pull-up is active during s1 of the instruction cycle. port 3 pins also have various secondary functions that are described below. 3p 3.0/rxd i/o receiver data input (asynchronous) or data input/output (synchronous) in serial (uart) mode 4 p3.1/txd i/o transmitter data output (asynchronous) or clock output (synchronous) in serial (uart) mode 5 p3.2/ int0 io i0 t t0 int1 io i1 tt1 t0 convst io tc0iticcs 1011 io 1011 1 1 1 01 s11 10t io tiitcc 10t 11t io icc 10 st i i ts 111 11 i t 0t 11 1c0 i cic0sccons 1 1c1 i cic1sccons 1 v s svvv 11 n innctionscitions
rev. 0 ADUC814 ?15? pin no. mnemonic type * function 16 vref i/o reference input/output. this pin is connected to the internal reference through a switch and is the reference source for the analog-to-digital converter. the nominal internal reference voltage is 2.5 v, which appears at the pin. this pin can be used to connect an external reference to the analog-to-digital converter by setting adccon1.6 to 1.0. connect 0.1 ss tc io tsi st t1c1s iso io siisoio osi io siosiio scoc io scsisic t1 i icoi t o ocoi v s svvv iiooioioss nots 1st1c0 stcc1 1
rev. 0 c02748?0?5/02(0) printed in u.s.a. ?16? ADUC814 outline dimensions 28-lead tssop package (ru-28) dimensions shown in millimeters and (inches) 4.50 (0.177) 4.30 (0.169) 28 15 14 1 9.80 (0.386) 9.60 (0.378) 6.50 (0.256) 6.25 (0.246) pin 1 seating plane 0.15 (0.006) 0.05 (0.002) 0.30 (0.0118) 0.19 (0.0075) 0.65 (0.0256) bsc 1.10 (0.0433) max 0.20 (0.0079) 0.090 (0.0035) 0.70 (0.028) 0.50 (0.020) 8 0 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design

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